RF / Microwave Engineer
RF / Microwave Engineer with Analog IC design skills
M.Eng. ECE @ Oregon State · Seeking New Grad roles · Corvallis, OR
About Me
Ameya Tiwari
M.Eng. ECE · Oregon State University
I'm a Master's student in Electrical and Computer Engineering at Oregon State University, specializing in RF/microwave circuit design and analog IC design. I've designed and characterized coupled-line filters, low-noise amplifiers, and CMOS amplifiers — working from schematic and EM simulation through lab characterization on VNA and spectrum analyzer.
Outside of circuits, I love using AI tools to build — whether it's scripting test automation, prototyping ideas, or building this site itself. I think the engineers who combine hardware depth with AI-assisted workflows will define the next decade.
Education
M.Eng. Electrical & Computer Engineering
Oregon State University · 2024 – Present
B.E. Electrical Engineering
India · Prior to 2024
Work
Designed a 3 GHz BPF in ADS and HFSS: translated prototype element values into physical coupled-line dimensions, iterated layout via S11/S21 results, and characterised the fabricated board with a VNA, spectrum analyser, and RF source.
3 GHz · ADS · HFSS · VNA
2.4 GHz LNA for 5G/Wi-Fi 6 front-end modules with input/output matching using Smith-chart tuning.
2.4 GHz · Gain 11.5 dB · NF 0.94 dB · IIP3 4.1 dBm
S-parameter analysis, impedance matching networks, and stub tuner simulations in Keysight ADS up to 20 GHz. Full-wave EM verification with ADS Momentum. Automated VNA/oscilloscope data acquisition via LabVIEW for repeatable, bench-time-efficient measurements.
Up to 20 GHz · ADS Momentum · LabVIEW Automation
1.8 V telescopic cascode op-amp — a foundational topology for RFIC front-end and analog baseband blocks. Applied gm/ID methodology for device sizing, Miller compensation, and HD3 analysis via a transient-to-DFT workflow in Cadence Spectre.
1.8 V · Gain 109 dB · UGB 288 MHz · HD3 < −50 dB
Dominant and non-dominant pole analysis via high-impedance node modelling — techniques directly applicable to RF amplifier bandwidth and stability design. Miller capacitor sizing (Cc = 0.3–1×CL) and Rz = 1/gm2 zero cancellation for improved phase margin.
Miller Comp · Phase Margin Tuning · Pole-Zero Analysis
Background
Oregon State University · Corvallis, OR
Oregon State University · OR, USA
L&T EdTech · India
Toolkit
Credentials
Anthropic
Issued May 2026
Qualcomm
Amazon Web Services
Download
Two versions tailored to different openings — pick the one that matches your role.
Primary focus
RF + Analog IC breadth
Get in Touch
Open to new-grad opportunities in RF / Microwave and Analog IC design. Reach out any time.